This invention relates to a voltage translator, particularly of the CMOS type.
Specifically, the invention relates to a CMOS voltage translator that has a differential cell circuit portion connected between first and second supply voltage references, and first and second transistor pairs connected together in series between the supply voltage references.
As is known, voltage translators are used in several applications, especially in integrated circuits, for the purpose of bringing a supply voltage of relatively low level (typically 3.3 to 5 V) to conveniently higher and/or lower values dependent on the requirements of various circuitry connected to the voltage supply.
A voltage translator is applied to a MOS transistor, where a high voltage may impair its reliability by causing the gate oxide to break down.
A prior solution, wherein an upper limit is placed on the value of the high-voltage supply, is shown generally in FIG. 1A and in more detail in FIG. 1B. A conventional voltage translator 1, being supplied a high-voltage reference VDDHIGH, is input a reference voltage VREF obtained from a voltage divider 2, with the latter being supplied with the high-voltage reference VDDHIGH and an input signal VIN.
It should be noted that the high-voltage reference VDDHIGH lies, for example, above the highest voltage value that can be applied to a MOS transistor.
In particular, the high-voltage reference VDDHIGH is applied to a first pair of P-type MOS transistors, MP1 and MP2, which are cross-connected together such that their gate and drain terminals are respectively connected to the source terminals of a second pair of P-type MOS transistors, MP3 and MP4. The gate terminals of the second transistor pair receive a reference voltage VREF from the voltage divider 2.
Also, the drain terminals of the second transistor pair MP3, MP4 are respectively connected to the source terminals of a pair of N-type MOS transistors, MN1 and MN2, whose gate terminals are driven respectively by the input signal VIN, presented at an input terminal IN of the voltage translator 1, and its inverse, i.e., a low-voltage reference VDDLOW obtained from an inverter INV which is connected between the input terminal IN and the gate terminal of the transistor MN2. The voltage translator 1 also has an output terminal OUT coinciding with the drain terminal of the transistor MP3.
Furthermore, the bulk terminals of the transistors MP1, MP2, MP3 and MP4 are connected to the high-voltage reference VDDHIGH.
As shown in FIG. 1B, the voltage divider 2 comprises first and second P-type MOS transistors, MP5 and MP6, in a diode configuration, which transistors are connected, in series with each other, between the high-voltage reference VDDHIGH and a ground reference GND.
In the instance of the transistors MP5 and MP6 being selected identical with each other, a value of the reference voltage VREF is obtained which is half that of the high voltage VDDHIGH, namely:
VREF=VDDHGH/2.
The operation of the voltage translator 1 under different operational conditions will now be reviewed.
In the event of the value of an input signal VIN applied to the input terminal IN being equal to that of the low-voltage reference VDDLOW, the drain terminals of the transistors MP1 and MP3 would be at VDDHIGH, and the drain terminals of the transistors MP4 and MP2 would be at GND and VDDHIGH+Vth(MP4), respectively, where Vth(MP4) is the threshold voltage value of the transistor MP4.
It should be noted that the terminals of all P-type MOS transistors have a voltage drop of VDDHIGH+Vth(PMOS), where Vth(PMOS) is the threshold voltage value of a PMOS transistor. This value is usually suitable for supply to the transistors under consideration. Otherwise, additional stages of the cascode type, that is additional pairs of PMOS transistors in the same configuration as transistors MP3 and MP4, would have to be provided.
It should also be noted that the drain terminal of transistor MN1 would be at VDDHIGH, this value being an acceptable one only because NMOS transistors of the drift type are used instead of standard NMOS transistors.
When the input signal VIN at the input terminal IN is changed from a value equal to GND to a value equal to the low-voltage supply reference VDDLOW, the drain terminal of the transistor MN1 is brought down to GND, and the source terminal of the transistor MP3 up to the value of VREF+Vth(MP3), where Vth(MP3) is the threshold voltage value of the transistor MP3; as the voltage across the gate and source terminals of the transistor MP3 drops below the threshold voltage Vth(MP3) of the transistor MP3, the latter is turned off.
Likewise, when the voltage value, equal to VDDHIGHxe2x88x92VREF+Vth(MP3), across the gate and source terminals of the transistor MP2 rises above the value of the threshold voltage of the latter, the transistor MP2 is turned on and the transistor MP1 turned off; the value of the voltage at the output terminal OUT of the voltage translator 1 rises to the high voltage VDDHIGH.
In this condition of operation, the greatest drop in voltage across the terminals of the PMOS transistors comprising the voltage translator 1 would still be VDDHIGH+Vth(PMOS).
Thus, a prerequisite for the voltage translator 1 to operate correctly, is that all the PMOS transistors contained in it should be capable of withstanding that voltage maximum on their gate oxides.
Another prior solution is shown generally in FIG. 2A and in more detail in FIG. 2B. Similar elements carry the same reference numerals and will not be described further.
In particular, it can be seen that an intermediate voltage translator 3 has been connected between the voltage translator 1 and the voltage divider 2, which intermediate translator 3 is supplied a high reference voltage VREFHIGH generated from a voltage source 3 for low-impedance loads, itself connected to the high-voltage reference VDDHIGH.
The intermediate translator 3 is input the reference voltage VREF and the input signal VIN, and supplies first and second intermediate reference voltages, VREF and VREF2, to the translator 1. The voltage translator 1 is further input the high reference voltage VREFHIGH.
In particular, the intermediate translator 3 is configured same as the translator 1, but is supplied the high reference voltage VREFHIGH.
In particular, this high reference voltage VREFHIGH is supplied to a first pair of P-type MOS transistors, M14 and M15, which are cross-connected together such that their gate and drain terminals are respectively connected to the source terminals of a second pair of P-type MOS transistors, M12 and M13. The gate terminals of the second transistor pair receive a reference voltage VREF from the voltage divider 2.
The drain terminals of the second transistor pair M12, M13 are respectively connected to the source terminals of a further pair of N-type MOS transistors, M11 and M10, having their gate terminals driven respectively by the input signal VIN, presented at an input terminal IN of the voltage translator 1, and its inverse, i.e., a low-voltage reference VDDLOW obtained from a further inverter INV being connected between the input terminal IN and the gate terminal of the transistor MN2.
The intermediate translator 3 has a first output terminal OUT1 coinciding with the drain terminal of the transistor M14, and has a second output terminal OUT2 coinciding with the drain terminal of the transistor M15. In particular, the first output terminal OUT1 is to supply said first intermediate reference voltage VREF1 to the gate terminal of the transistor MP4 in the voltage translator 1, and the second output terminal OUT2 is to supply said second intermediate reference voltage VREF2 to the gate terminal of the transistor MP3 in the voltage translator 1.
Lastly, yet another pair of PMOS transistors, MP9 and MP10, are connected between the first PMOS transistor pair MP1, MP2 and the second PMOS transistor pair MP3, MP4 of the voltage translator 1. The transistors MP9 and MP10 have their gate terminals connected together and connected to the voltage reference VREFHIGH from the voltage source 4.
The configuration shown in FIGS. 2A and 2B is essentially a cascade of voltage translators such as the conventional translator 1, with intermediate voltage references for dealing with the low-impedance nodes. In particular, the values of the first and second intermediate reference voltages, VREF1 and VREF2, depend on the values taken by the input voltage VIN.
In actual practice, however, the first intermediate reference voltage should have an extremely low output impedance to allow the intermediate translator to perform as expected.
The underlying technical problem of this invention is to provide a voltage translator that can accept great voltage drops across the oxide terminals of its PMOS transistors, and that exhibits structural and functional features appropriate to overcome the limitations with which prior voltage translators are beset.
The principle on which the disclosed embodiment of the invention stands is one of having the values of internally generated reference voltages VREF1 and VREF2 regulated automatically, using a pair of voltage dividers and cascoded voltage-translating stages.
Based on this principle, the technical problem is solved by a CMOS voltage translator having a differential cell circuit portion connected between first and second supply voltage references, and having first and second transistor pairs connected together in series between said supply voltage references, further including a first divider of the first supply voltage reference for producing a first reduced supply voltage reference on a first internal circuit node, and a second divider of the first supply voltage reference for producing a second reduced supply voltage reference on a second internal circuit node. A multiplexer circuit portion connected between the first and second reduced supply voltage references is provided to deliver first and second reference voltages to the differential cell circuit portion on third and fourth internal circuit nodes, respectively.
The features and advantages of a disclosed embodiment of a voltage translator according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.